The present invention relates to integrated circuit devices and, more particularly, to duty cycle circuits and methods for integrated circuit devices.
It is know for various integrated circuit devices to utilize a duty cycle correcting circuit to adjust the duty cycle of an output clock signal on the integrated circuit device to fifty percent (50%). The duty cycle correcting circuit may include a duty cycle corrector and a duty cycle detector. As used herein, “duty cycle” refers to a ratio of a pulse width with respect to a pulse cycle of a clock signal.
FIG. 1 is a block diagram illustrating a conventional duty cycle correcting circuit. The duty cycle correcting circuit illustrated in FIG. 1 includes a duty cycle corrector 10, a duty cycle detector 12, and a signal transmission path portion 14. The duty cycle corrector 10 generates a corrected clock signal pair OUT and OUTB responsive to a voltage difference between an input clock signal pair ICLK and ICLKB and first and second duty detecting signals C and CB, which are output from the duty cycle detector. The duty cycle detector 12 detects a duty cycle of the output clock signal pair OCLK and OCLKB and generates the first and second detecting signals C and CB. The signal transmission path portion 14 receives the corrected clock signal pair OUT and OUTB to generate the output clock signal pair OCLK and OCLKB with a corrected duty cycle.
A gain of the conventional duty cycle correcting circuit is determined by multiplying a gain of the duty cycle corrector 10 by a gain of the duty cycle detector 12. A duty cycle correcting range of the duty cycle correcting circuit of FIG. 1 is directly proportional to the gain thereof and a jitter of a signal from the circuit is inversely proportional to the gain. In other words, when a gain of the duty cycle correcting circuit of FIG. 1 is large, a duty cycle correcting range thereof is increased and a jitter of a signal therefrom becomes larger based on a response characteristic and a signal to noise ratio (SNR) thereof. As the gain decreases, the duty cycle correcting range is reduced and the jitter becomes smaller based on the response characteristic and signal to noise ratio (SNR).
For the circuit of FIG. 1, when the frequency of the input clock signal is high, the desired duty cycle correcting range is generally decreased. On the other hand, when the frequency of the input clock signal is low, the desired duty cycle correcting range is generally increased. Thus, if a frequency of the input clock signal is a low frequency, an increased duty cycle correcting range is typically desired as contrasted with a high frequency input clock signal.
The conventional duty cycle correcting circuit of FIG. 1 may have a problem operating stably with a clock signal having a wide frequency range as its gain is typically fixed. In other words, if provided a high gain, a conventional circuit like that of FIG. 1 may have an increased duty cycle correcting range for stable operation when a low frequency clock signal is applied but, when a high frequency clock signal is applied, the circuit may become sensitive to noise and may not operate stably. In contrast, if provided a low gain, the circuit of FIG. 1 may be insensitive to noise and operate stably when a high frequency clock signal is applied but the circuit may have a reduced duty cycle correcting range. As a result, the circuit may not operate stably when a low frequency clock signal is applied.